Recently, a ferroelectric memory system is proposed in which a capacitance film of a ferroelectric material is disposed in a capacitor of a memory cell so as to make stored data nonvolatile. A ferroelectric material is a material having a characteristic of polarization changed in accordance with a change in the polarity of a voltage (an electric field) in a hysteresis loop as is shown in FIG. 20. Specifically, in a ferroelectric material, as an applied voltage (electric field) is increased, the polarization is increased along a change curve and reaches a saturation polarization value at a point A, and as the voltage (electric field) is decreased, the polarization is gradually decreased not through the above-described change process, and even when the electric field becomes 0, the polarization does not become 0 but residual polarization at a point B remains. When a negative electric field is applied to a ferroelectric material and the electric field is increased in the negative direction, a saturation polarization value is attained at a point C, and when the electric field is decreased to 0, residual polarization at a point D remains. In this manner, a ferroelectric material has a characteristic that residual polarization remains in accordance with the strength and the polarity of an electric field applied theretofore, namely, the so-called hysteresis characteristic. At this point, a saturation polarization value corresponds to a point where the two change curves in the hysteresis curve of FIG. 20 become substantially the same curve, namely, a point where these curves are substantially in contact with each other. Furthermore, the behavior of polarization inversion depends not upon a voltage but upon an electric field given as a value obtained by dividing a voltage by a film thickness, but in the following description, the thickness of a ferroelectric film is fixed, and hence, an operation characteristic in accordance with a voltage will be described.
Therefore, when a ferroelectric capacitor including a ferroelectric film sandwiched between two conductive films is provided in a memory cell and residual polarization of the ferroelectric film in accordance with the polarity and the amplitude of a signal voltage is used as stored data, the stored data can be nonvolatile, and thus, the so-called nonvolatile memory system can be realized.
For example, U.S. Pat. No. 4,873,664 discloses the following two types of ferroelectric memory systems:
In the first type of the nonvolatile memory system, a memory cell includes one transistor and one ferroelectric capacitor (1T1C) per bit. In this case, one dummy memory cell (reference cell) is provided to, for example, every 256 main memory cells (normal cells).
In the second type of the nonvolatile memory system, no dummy memory cell is provided and a memory cell includes two transistors and two ferroelectric capacitors (2T2C) per bit. In this case, a pair of complementary data are stored in a pair of ferroelectric capacitors.
Furthermore, as is disclosed in, for example, U.S. Pat. No. 4,888,733, a memory cell can include two transistors and one ferroelectric capacitor (2T1C) per bit.
Moreover, as a ferroelectric material used in a ferroelectric capacitor, KNO.sub.3, PbLa.sub.2 O.sub.3 --ZrO.sub.2 --TiO.sub.2, PbTiO.sub.3 --PbZrO.sub.3 and the like are known. Furthermore, PCT International Publication No. WO93/12542 discloses a ferroelectric material suitable to a ferroelectric capacitor used in a ferroelectric memory system that is much less fatigued than PbTiO.sub.3 --PbZrO.sub.3.
On the other hand, ferroelectric materials generally used at present cannot be free from fatigue, and when they are used for a long period of time, their ability to store data can be spoiled.
Therefore, as is disclosed in U.S. Pat. No. 5,532,953, in order not to spoil the ability to store data through usage for a long period of time, a technique to write data at a voltage sufficient for completely saturating a ferroelectric capacitor is used.
Now, the structure and the operation of a ferroelectric memory system disclosed in this publication will be described.
FIG. 21 is an electric circuit diagram for showing the configuration of a memory cell portion of the conventional ferroelectric memory system. In FIG. 21, between a bit line 124 and an inverted bit line 126 and a cell plate line 122 in a memory cell 110, memory cell transistors 112 and 114 and memory cell capacitors 116 and 118 are serially disposed. The gates of the memory cell transistors 112 and 114 are connected with a word line 120. Furthermore, for example, with one of the memory cell capacitors supplied with the residual polarization at the point B (H data) of FIG. 20, and with the other memory cell capacitor supplied with the residual polarization at the point D (L data) of FIG. 20, the polarized state of these two memory capacitors is regarded as data "1". Also, with each of the memory cell capacitors placed in the opposite polarized state to the polarized state of data "1", this opposite polarized state is stored as data "0". By utilizing such complementary data, a ferroelectric memory system with high reliability can be obtained.
Next, read, write (including rewrite) and recovery operations of the conventional ferroelectric memory system will be described. FIGS. 22(a) and 22(b) are flowcharts described in the aforementioned publication as FIGS. 4A and 4B. As is shown in FIG. 22(a), at times t3 and t4, data is read by releasing the charges of the memory cell capacitors 112 and 114 onto the bit line 124 and the inverted bit line 126, and at a time t5, a voltage difference between the bit line 124 and the inverted bit line 126 is sensed through amplification to logical values H and L. Next, at a time t6, a charge pump is operated so as to increase the supply voltage from 4 V to 6 V. Then, by utilizing the increased supply voltage, a write operation is conducted at the time t6. Through the aforementioned procedures, read, sense and write operations are conducted.
Also, as is shown in FIG. 22(b), read, sense and recovery operations are conducted through similar procedures. A recovery operation is an operation for returning the polarized state of a ferroelectric capacitor to a state prior to a read operation.
At this point, the aforementioned publication describes that a write pulse and a release pulse have a width of 20 nanoseconds, and that a read pulse has substantially the same width.
In this manner, in the above-described conventional ferroelectric memory system, a write operation is conducted under application of a voltage necessary for completely saturating a capacitor of a ferroelectric capacitor (the point A of FIG. 20). Specifically, a write operation is conducted at the high voltage (6 V) increased by the charge pump. By adopting such a writing method, the data holding performance of the ferroelectric memory system is to be improved and the life is to be elongated.